Improving parallel system performance by changing the arrangement of the network links
Proceedings of the 14th international conference on Supercomputing
A new routing mechanism for networks with irregular topology
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
A New Communication Mechanism for Cluster Computing
Euro-Par '01 Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing
Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
An overview of the BlueGene/L Supercomputer
Proceedings of the 2002 ACM/IEEE conference on Supercomputing
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism
Proceedings of the 31st annual international symposium on Computer architecture
A Routing Methodology for Achieving Fault Tolerance in Direct Networks
IEEE Transactions on Computers
FRoots: A Fault Tolerant and Topology-Flexible Routing Technique
IEEE Transactions on Parallel and Distributed Systems
Increasing the throughput of an adaptive router in network-on-chip (NoC)
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Rotary router: an efficient architecture for CMP interconnection networks
Proceedings of the 34th annual international symposium on Computer architecture
Analysis of photonic networks for a chip multiprocessor using scientific applications
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Blue Gene/L torus interconnection network
IBM Journal of Research and Development
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
Prevention flow-control for low latency torus Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A vertical bubble flow network using inductive-coupling for 3-D CMPs
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
The IBM Blue Gene/Q interconnection network and message unit
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
A new adaptive fault-tolerant routing methodology for direct networks
HiPC'04 Proceedings of the 11th international conference on High Performance Computing
Enforcing dimension-order routing in on-chip torus networks without virtual channels
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
Looking under the hood of the IBM blue gene/Q network
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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A router design for torus networks that significantly reduces message latency over traditional wormhole routers is presented in this paper. This new router implements virtual cut-through switching and fully-adaptive minimal routing. Packet deadlock is avoided by providing escape ways governed by Bubble flow control, a mechanism that guarantees enough free buffer space in the network to allow continuous packet movement.Both deterministic and adaptive Bubble routers have been designed in VLSI using VHDL synthesis tools. Adopting a fair quantitative comparison, we demonstrate that Bubble routers exhibit a reduction in base latency values over 40% with respect to the corresponding wormhole routers, without any penalty in network throughput. With much lower VLSI costs than adaptive wormhole routers, the adaptive Bubble router is even faster than deterministic wormhole routers based on virtual channels.