Reliability-Centric Hardware/Software Co-Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Reliability-aware Co-synthesis for Embedded Systems
Journal of VLSI Signal Processing Systems
Specification and design considerations for reliable embedded systems
Proceedings of the conference on Design, automation and test in Europe
An ILP formulation for task scheduling on heterogeneous chip multiprocessors
ISCIS'06 Proceedings of the 21st international conference on Computer and Information Sciences
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This paper presents an approach for designing embedded systems able to tolerate hardware faults, defined as an evolution of our previous work proposing an hardware/software co-design framework for realizing reliable embedded systems. The framework is extended tosupport the designer in achieving embedded systems with fault tolerant properties minimizing overheads and limiting power consumption. A reference system architecture is proposed; the specific hardware/software implementation and reliability methodologies (to achieve the fault tolerance properties) are the result of an enhanced hw/sw partitioning process driven by the designer' constraints and by the reliability constraints, set at the beginning of the designprocess. By introducing also the reliability constraints during specification, the final system can benefit from the introduced redundancy also for performance gains, while limiting area, time, performance and power consumption overheads.