TOWARDS A UNIFIED TEST PROCESS: FROM UML TO END-OF-LINE FUNCTIONAL TEST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
System-on-chip validation using UML and CWL
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Creating and Validating Embedded Assertion Statecharts
IEEE Distributed Systems Online
Transformation and Verification of Executable UML Models
Electronic Notes in Theoretical Computer Science (ENTCS)
Architectural design, behavior modeling and run-time verification of network embedded systems
Proceedings of the 12th Monterey conference on Reliable systems on unreliable networked platforms
Model-driven protocol design based on component oriented modeling
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Aligning UML 2.0 state machines and temporal logic for the efficient execution of services
ODBASE'06/OTM'06 Proceedings of the 2006 Confederated international conference on On the Move to Meaningful Internet Systems: CoopIS, DOA, GADA, and ODBASE - Volume Part II
On the formalization of UML activities for component-based protocol design specifications
SOFSEM'12 Proceedings of the 38th international conference on Current Trends in Theory and Practice of Computer Science
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The Unified Modeling Language UML is well suited for the design of real-time systems. In particular, interaction diagrams and statecharts support the design of dynamic system behaviors. Real-time aspects of behaviors can be described by time constraints. The semantics of the UML, however, is non-formal.In order to enable formal design verification, we therefore propose to complement the UML based design by additional formal models which refine UML diagrams to precise formal models. We apply the formal specification technique cTLA, which is based on L. Lamport's Temporal Logic of Actions TLA. In particular cTLA supports modular definitions of process types and the composition of systems from coupled process instances.Since process composition has superposition character, each process system has all of the relevant properties of its constituting processes. Therefore mostly small subsystems are sufficient for the verification of system properties and it is not necessary to use complete and complex formal system models. We present this approach by means of an example and also exemplify the formal verification of its hard real-time properties.