Prediction of interconnect pattern density distribution: derivation, validation, and applications
Proceedings of the 2003 international workshop on System-level interconnect prediction
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Metal-density driven placement for cmp variation and routability
Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
The importance of an interconnect pattern densitymodel in ASIC design flow for a 90nm technology ispresented. It is shown that performing the timing analysisat the worst-case corner model for interconnect variation,without the knowledge of interconnect pattern density,often results in overdesign. Our experiments on real ASICproducts indicate that knowledge of interconnect patterndensity in timing analysis of 90nm ASIC design flowprevents such overdesign. Quantitatively, it is shown thatconsidering only the worst-case corner model in a globalnet results in a 10% delay overdesign. To meet the targetdelay for the net, it is sufficient to use a 45% smaller gate,which results in a 32% reduction in gate powerdissipation, as well. It is, therefore, imperative to takeinto account the interconnect pattern density informationin ASIC design flow of 90nm and future technologies.