Optimizing an ANSI C interpreter with superoperators
POPL '95 Proceedings of the 22nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Stack caching for interpreters
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Optimizing direct threaded code by selective inlining
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
A code compression system based on pipelined interpreters
Software—Practice & Experience
Optimising Bytecode Emulation for Prolog
PPDP '99 Proceedings of the International Conference PPDP'99 on Principles and Practice of Declarative Programming
Vmgen: a generator of efficient virtual machine interpreters
Software—Practice & Experience
Dynamic Bytecode Usage by Object Oriented Java Programs
TOOLS '99 Proceedings of the Technology of Object-Oriented Languages and Systems
The case against stack-oriented instruction sets
ACM SIGARCH Computer Architecture News
A portable research framework for the execution of java bytecode
A portable research framework for the execution of java bytecode
SableVM: a research framework for the efficient execution of java bytecode
JVM'01 Proceedings of the 2001 Symposium on JavaTM Virtual Machine Research and Technology Symposium - Volume 1
Effective inline-threaded interpretation of Java bytecode using preparation sequences
CC'03 Proceedings of the 12th international conference on Compiler construction
Combining stack caching with dynamic superinstructions
Proceedings of the 2004 workshop on Interpreters, virtual machines and emulators
Interpreting programs in static single assignment form
Proceedings of the 2004 workshop on Interpreters, virtual machines and emulators
Virtual machine showdown: stack versus registers
Proceedings of the 1st ACM/USENIX international conference on Virtual execution environments
Proceedings of the third ACM SIGPLAN conference on History of programming languages
Virtual machine showdown: Stack versus registers
ACM Transactions on Architecture and Code Optimization (TACO)
VEP: a virtual machine for extended proof-carrying code
Proceedings of the 1st ACM workshop on Virtual machine security
Byte code level cross-compilation for developing web applications
Science of Computer Programming
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Cross-compiling Android applications to the iPhone
Proceedings of the 8th International Conference on the Principles and Practice of Programming in Java
An extended proof-carrying code framework for security enforcement
Transactions on computational science XI
AMaχoS: abstract machine for Xcerpt: architecture
PPSWR'06 Proceedings of the 4th international conference on Principles and Practice of Semantic Web Reasoning
Swift: a register-based JIT compiler for embedded JVMs
VEE '12 Proceedings of the 8th ACM SIGPLAN/SIGOPS conference on Virtual Execution Environments
Challenges for a trace-based just-in-time compiler for haskell
IFL'11 Proceedings of the 23rd international conference on Implementation and Application of Functional Languages
Cross-compiling Java to JavaScript via tool-chaining
Proceedings of the 2013 International Conference on Principles and Practices of Programming on the Java Platform: Virtual Machines, Languages, and Tools
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Virtual machines (VMs) are a popular target for language implementers. Conventional wisdom tells us that virtual stack architectures can be implemented with an interpreter more efficiently, since the location of operands is implicit in the stack pointer. In contrast, the operands of register machine instructions must be specified explicitly. In this paper, we present a working system for translating stack-based Java virtual machine (JVM) code to a simple register code. We describe the translation process, the complicated parts of the JVM which make translation more difficult, and the optimisations needed to eliminate copy instructions. Experimental results show that a register format reduces the number of executed instructions by 34.88%, while increasing the number of bytecode loads by an average of 44.81%. Overall, this corresponds to an increase of 2.32 loads for each dispatch removed. We believe that the high cost of dispatches makes register machines attractive even at the cost of increased loads.