The Min-cut shuffle: toward a solution for the global effect problem of Min-cut placement
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
A portable and extendible testbed for distributed logic simulation
EURO-DAC '94 Proceedings of the conference on European design automation
A timing driven N-way chip and multi-chip partitioner
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Glue-logic partitioning for floorplans with a rectilinear datapath
EURO-DAC '91 Proceedings of the conference on European design automation
Towards optimizing global MinCut partitioning
EURO-DAC '91 Proceedings of the conference on European design automation
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We introduce a generalization of the min-cut partitioning problem, called Min-Cost Tree Partitioning, in which the nodes of an hypergraph G are to be mapped on to the vertices of a tree structure T, and the cost function to be minimized is the cost of routing the hyperedges (i.e., the nets) of G on the edges of T. We discuss several interesting VLSI design applications for this problem. We describe an iterative improvement heuristic for solving this problem.