Glue-logic partitioning for floorplans with a rectilinear datapath

Authors:
Allen C. H. Wu;Daniel D. Gajski
Affiliations:
University of California, Irvine, CA;University of California, Irvine, CA
Venue:
EURO-DAC '91 Proceedings of the conference on European design automation
Year:
1991

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Abstract

This paper describes a novel glue-logic partitioning algorithm for floorplan generation in a constrainted rectilinear area. This algorithm dissects the layout area into area blocks according to the given module aspect ratio. The algorithm estimates the transistor capacity for each area block, and then uses a seed-based multiway partitioning strategy to assign glue-logic components into area blocks. The algorithm runs iteratively and selects the partition with the minimum total area as the final floorplan. The examples demonstrate the algorithm's suitability for top-down hierarchical physical design.