Multicast traffic in input-queued switches: optimal scheduling and maximum throughput

  • Authors:

  • Marco Ajmone Marsan;Andrea Bianco;Paolo Giaccone;Emilio Leonardi;Fabio Neri

  • Affiliations:

  • Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy;Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy;Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy;Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy;Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy

  • Venue:
  • IEEE/ACM Transactions on Networking (TON)
  • Year:
  • 2003

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Abstract

This paper studies input-queued packet switches loaded with both unicast and multicast traffic. The packet switch architecture is assumed to comprise a switching fabric with multicast (and broadcast) capabilities, operating in a synchronous slotted fashion. Fixed-size data units, called cells, are transferred from each switch input to any set of outputs in one time slot, according to the decisions of the switch scheduler, that identifies at each time slot a set of nonconflicting cells, i.e., cells neither coming from the same input, nor directed to the same output.First, multicast traffic admissibility conditions are discussed, and a simple counterexample showing intrinsic performance losses of input-queued with respect to output-queued switch architectures is presented. Second, the optimal scheduling discipline to transfer multicast packets from inputs to outputs is defined. This discipline is rather complex, requires a queuing architecture that probably is not implementable, and does not guarantee in-sequence delivery of data. However, from the definition of the optimal multicast scheduling discipline, the formal characterization of the sustainable multicast traffic region naturally follows. Then, several theorems showing intrinsic performance losses of input-queued with respect to output-queued switch architectures are proved. In particular, we prove that, when using per multicast flow FIFO queueing architectures, the internal speedup that guarantees 100% throughput under admissible traffic grows with the number of switch ports.