Multicast ATM switches: survey and performance evaluation
ACM SIGCOMM Computer Communication Review
Multicast Scheduling for Switches with Multiple Input-Queues
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
Multicast traffic in input-queued switches: optimal scheduling and maximum throughput
IEEE/ACM Transactions on Networking (TON)
FIFO-Based Multicast Scheduling Algorithm for Virtual Output Queued Packet Switches
IEEE Transactions on Computers
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
On the Integration of Unicast and Multicast Cell Scheduling in Buffered Crossbar Switches
IEEE Transactions on Parallel and Distributed Systems
Internet-Router Buffered Crossbars Based on Networks on Chip
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Asymptotic Performance Limits of Switches With Buffered Crossbars Supporting Multicast Traffic
IEEE Transactions on Information Theory
Multicast scheduling for input-queued switches
IEEE Journal on Selected Areas in Communications
Microprocessors & Microsystems
Efficient multicast schemes for 3-D Networks-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
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The Internet growth coupled with the variety of its services is creating an increasing need for multicast traffic support by backbone routers and packet switches. Recently, buffered crossbar (CICQ) switches have shown high potential in efficiently handling multicast traffic. However, they were unable to deliver optimal performance despite their expensive and complex crossbar fabric. This paper proposes an enhanced CICQ switching architecture suitable for multicast traffic. Instead of a dedicated internal crosspoint buffer for every input-output pair of ports, the crossbar is designed as a multi-hop Network on Chip (NoC). Designing the crossbar as a NoC offers several advantages such as low latency, internal fabric load balancing and path diversity. It also obviates the requirement of the virtual output queuing by allowing simple FIFO structure withouts performance degradation. We designed appropriate routing for the NoC as well as on-chip router scheduling and tested its performance under a wide range of input multicast traffic. Simulations results showed that our proposal outperforms the CICQ architecture and offers a viable architectural alternative. We also studied the effect of various parameters such as the depth of the NoC as well as the speedup requirement for high-bandwidth multicast switching.