Regular Realization of Symmetric Functions Using Reversible Logic

  • Authors:
  • Marek Perkowski;Malgorzata Chrzanowska-Jeske;Alan Mishchenko;Xiaoyu Song;Anas Al-Rabadi;Bart Massey;Pawel Kerntopf;Andrzej Buller;Lech Jozwiak;Alan Coppola

  • Affiliations:
  • -;-;-;-;-;-;-;-;-;-

  • Venue:
  • DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
  • Year:
  • 2001

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Abstract

Abstract: Reversible logic is of increasing importance to many future computer technologies. We introduce a regular structure to realize symmetric functions in binary reversible logic. This structure, called a 2 * 2 net structure, allows for a more efficient realization of symmetric functions than the methods introduced by the other authors. Our synthesis method allows us to realize arbitrary symmetric function in a completely regular structure of reversible gates with relatively little "garbage". Because every Boolean function can be made symmetric by repeating input variables, our method is applicable to arbitrary multi-input multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of additional gate outputs. The method can be also used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs.