Two economical directory schemes for large-scale cache coherent multiprocessors
ACM SIGARCH Computer Architecture News
Design of an Adaptive Cache Coherence Protocol for Large Scale Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
A novel JAVA processor for embedded devices
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
HISC: A computer architecture using operand descriptor
Computers and Electrical Engineering
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The access control on data is usually on per memory page basis and is implemented in the Translation Lookaside Buffer (TLB) via page tables managed by memory management of operating systems. In addition, to optimize the memory reference performance, it is desirable to specify if a page should be encached or not, so that unnecessary and undesirable data encaching will be avoided. It is also desirable to be able to specify if maintaining data coherency in a multiprocessing system is required. Such maintenance demands a lot of checking, which creates performance bottlenecks and system complexity, but only a small percentage of data requires absolute data coherency. In all these cases, pages are not logical entities for such attributes or characteristic assignments. Better choices are the operands, which can map directly to the variables in a program.In this paper, we are proposing an architecture to support the access control, the maintenance requirement of data coherency and optional encaching on data as system attributes on individual operands.