Design Diversity for Concurrent Error Detection in Sequential Logic Circuts

Authors:
Subhasish Mitra;Edward J. McCluskey
Affiliations:
-;-
Venue:
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Year:
2001

Citing 0
Cited 4

A Design Diversity Metric and Analysis of Redundant Systems

IEEE Transactions on Computers
Techniques for Estimation of Design Diversity for Combinational Logic Circuits

DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Efficient Design Diversity Estimation for Combinational Circuits

IEEE Transactions on Computers
Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs

Microprocessors & Microsystems

Quantified Score

Hi-index	0.01

Visualization

Abstract

We present a technique using diverse duplication to implement concurrent error detection (CED) in sequential logic circuits. We examine three different approaches for this purpose: (1) Identical state encoding of the two sequential logic implementations, duplication of flip-flops, diverse implementation of the combinational logic part (output logic and next-state logic) and comparators on flip-flop outputs and primary outputs; (2) Diverse state encoding of the two implementations, duplication of flip-flops, diverse combinational logic implementation and comparators on primary outputs only; and (3) Identical state encoding, parity prediction for the flip-flops, diverse combinational logic implementation, comparators on primary outputs and parity checkers on flip-flop outputs. Our results for the simulated sequential benchmark circuits demonstrate that the third approach is most efficient in protecting sequential logic circuits against multiple and common-mode failures. The computational complexity of the data integrity analysis of the third approach is of the same order as that of the first approach and is at least an order of magnitude less than that of the second approach.