A coupled hardware and software architecture for programmable digital signal processors (synchronous data flow)

Determining the Order of Processor Transactions in StaticallyScheduled Multiprocessors

Journal of VLSI Signal Processing Systems

RRES: a novel approach to the partitioning problem for a typical subset of system graphs

EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign

Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures

Proceedings of the twenty-second annual ACM symposium on Parallelism in algorithms and architectures

Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors

HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers

Adaptive task duplication using on-line bottleneck detection for streaming applications

Proceedings of the 9th conference on Computing Frontiers