ITCC '00 Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00)
Cost-effective video filtering solution for real-time vision systems
EURASIP Journal on Applied Signal Processing
Reconfigurable Morphological Image Processing Accelerator for Video Object Segmentation
Journal of Signal Processing Systems
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This article presents considerations concerning the choice of a multiprocessor unit architecture for fast realization of the tasks connected with initial processing of visual images. Basing on the earlier experience of the author within the scope of the real time systems, implementation in pipeline architecture of specialized hardware processor 驴 assembled on the basis of FPGA programmable structures 驴 was suggested. In particular, implementation of the following processor has been prepared: median filtration, convolution, look-up-table recording, logic processor, histogram count-up and morphological processors. Experimental work has also been done, in order to verify the concept assumed, whose results associated with delay times are included in the article. A structure of universal reconfigurable processor has been moreover offered. The works have been financed by the Polish Scientific Research Committee.