Integrated floorplanning, module-selection, and architecture generation for reconfigurable devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Customized kernel execution on reconfigurable hardware for embedded applications
Microprocessors & Microsystems
An area-efficient universal cryptography processor for smart cards
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Although domain-specialized FPGAs can offersignificant area, speed and power improvements overconventional reconfigurable devices, there are severalunique and unexplored design problems that complicatetheir development. One source of these problems is thatdesigners often opt to replace more universal, fine-grainlogic elements with a specialized set of coarse-grainfunctional units to improve computation speed and reducerouting complexity. One issue this introduces is that it isnot obvious how to simultaneously consider allapplications in a domain and determine the mostappropriate overall number and ratio of the differentfunctional units. In this paper, we illustrate how thisproblem manifests itself during the development of anencryption-specialized FPGA architecture. We presentthree algorithms that solve this problem by balancing thehardware needs of the domain while consideringperformance and area requirements. We believe theseconcerns need to be addressed by future CAD tools inorder to develop more sophisticated application-specializedreconfigurable devices.