Automatic translation of software binaries onto FPGAs
Proceedings of the 41st annual Design Automation Conference
An FPGA-based VLIW processor with custom hardware execution
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
EURASIP Journal on Applied Signal Processing
An overview of a compiler for mapping software binaries to hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Generation of control and data flow graphs from scheduled and pipelined assembly code
LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
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Hybrid architectures, which are composed of a conventionalprocessor closely coupled with reconfigurable logic,seem to combine the advantages of both types of hardware.They present some practical difficulties, however. Theinterface between the processor and the reconfigurablelogic is crucial to performance and is often difficult toimplement well. Partitioning the application between theprocessor and logic is a difficult task, typically complicatedby entirely different programming models, heterogeneousinterfaces to external resources, and incompatible representationsof applications. A separate executable must beproduced and maintained for each type of hardware. Anovel architecture called HASTE (Hybrid Architecturewith a Single Transformable Executable) solves many ofthese difficulties. HASTE allows a single executable to representan entire application, including portions that run ona reconfigurable fabric and portions that run on a sequentialprocessor. This executable can execute in its entirety onthe processor, but for best performance portions of theapplication are mapped onto the fabric at run-time. Theapplication representation is key to making this conceptviable, and several different ones were examined. Someused a relatively conventional register instruction setarchitecture (ISA) while others used a new queue-basedISA. An ISA using a modified form of register addressinghas been shown to have the best overall characteristics andshould allow for the practical implementation of HASTE.