Two widely-different architectural approaches to computer image generation

  • Authors:
  • H. W. Park;K. S. Eo;D. L. Kim;B. K. Choi;Y. Kim;T. Alexander

  • Affiliations:
  • University of Washington, Seattle, WA;University of Washington, Seattle, WA;University of Washington, Seattle, WA;University of Washington, Seattle, WA;University of Washington, Seattle, WA;University of Washington, Seattle, WA

  • Venue:
  • VIS '91 Proceedings of the 2nd conference on Visualization '91
  • Year:
  • 1991

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Abstract

Among several systems from the UWGSP (University of Washington Graphics System Processor) series, two recent architectures were designed for imaging and graphics, One of them, UWGSP3, has already been completed and is being used for selected applications, while the other one, UWGSP4, is being implemented now.These two systems use parallel and pipelined architectures for high performance graphics operations. UWGSP3 uses only commercially available of-the-shelf chips, and consists of a TMS34082 graphics system processor and four TMS34082 floating point coprocessor that can be configured into pipelined or SIMD modes depending on the algorithm. UWGSP4, however, uses dedicated ASIC (Application Specific IC) chips for higher performance, and consists of two main computational parts: a parallel vector processor with 16 vector processing units, used mainly for image processing, and a graphics subsystem which utilizes a parallel pipelined architecture for image synthesis.IN this paper, the computer graphics aspects of both UWGSP3 and UWGSP4 will be described.