Data structures and network algorithms
Data structures and network algorithms
Provably good routing in graphs: regular arrays
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
Experimental results for a linear program global router
Computers and Artificial Intelligence
Topics in the design and anaylsis of combinatorial algorithms
Topics in the design and anaylsis of combinatorial algorithms
LocusRoute: a parallel global router for standard cells
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A language for describing rectilinear Steiner tree configurations
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
A global router using an efficient approximate multicommodity multiterminal flow algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
FARM: an efficient feed-through pin assignment algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A new generalized row-based global router
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 international symposium on Physical design
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We describe a new global routing algorithm designed specifically for sea-of-gates circuits. The algorithm has been generalized to handle gate array and standard cell circuits. The main features of the algorithm are: (1) interconnection length minimization using a new Steiner tree generation method, (2) a two-stage coarse global routing method which seeks to even congestion, (3) a maze routing procedure which removes overflows and reduces the congestion, (4) vertical track assignment, and (5) congestion evening at the detailed global routing level. In tests on the MCNC benchmark circuits, the algorithm produced layouts with an average of 11% fewer routing tracks than the other algorithms. In tests on gate array benchmark circuits, the algorithm not only achieved uniform channel densities, but the maximum channel densities it produced are the lowest values that have ever been reported.