Validated observation and reporting of microscopic performance using Pentium II counter facilities

  • Authors:
  • Haleh Najafzadeh;Seth Chaiken

  • Affiliations:
  • University at Albany, State University of New York;University at Albany, State University of New York

  • Venue:
  • WOSP '04 Proceedings of the 4th international workshop on Software and performance
  • Year:
  • 2004

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Abstract

Microprocessors typically have software readable counters for events such as instruction executions, cycles, instruction stalls, and cache misses. Besides their usefulness to report overall performance metrics, these counters reveal details about dynamic process behavior and hardware affects of compiler optimizations. Our research develops and evaluates, in case studies, methodologies to determine just how accurate measurements from counters can be. We might then compensate for, reduce and/or estimate errors caused by the instrumentation or by system activity unrelated to the phenomena under study. We validate our flow-graph based perturbation model on small cases using static instruction counting, basic cache theory, and interrupt vs. cycle frequencies. We validate on larger cases using the existing Linux system calls, shells and user mode hardware counter access instructions. Our studies indicate so far that these performance factors, as related to specific machine code and data organization, can be directly observed in a practical/working system (Linux) with reasonable accuracy and that they can be quantitatively related to measurements of overall performance. Our current focus is on microscopic observations and phenomena because we seek to fully understand the capabilities and limitations of software accessible hardware self-reporting features of recent (Pentium II) technology.