PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
Migrating a CISC computer family onto RISC via object code translation
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Communications of the ACM
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Shade: a fast instruction-set simulator for execution profiling
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
DIGITAL FX!32: combining emulation and binary translation
Digital Technical Journal
Quality and speed in linear-scan register allocation
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Linear scan register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
An Architectural Framework for Runtime Optimization
IEEE Transactions on Computers
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
LaTTe: A Java VM Just-in-Time Compiler with Fast and Efficient Register Allocation
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
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Binary translation has been widely used as object codemigration across different architectures. Most currentworks are targeted towards running an existing (old architecture)binary version of a complex application on a newerarchitecture and so availability of resources is not a problem.In this paper we propose a technique called RABIT foremulating a newer architecture's binary on an older one.RABIT will allow the consumers to emulate the applicationsdeveloped for newer hardware on their older machines byincurring some performance trade-offs. This way the needyconsumers can take advantage of the newer software featureson their existing machines before they decide to upgradethem to later models. In situations where the newerhardware is in place, our technique can be used to run applicationsredundantly on the older machine for dependabilityanalysis. It also provides the CPU architects with aninstruction-level simulator to test the design and stability ofa new CPU before the new hardware is actually in place.RABIT's design consists of a translator, an interpreter anda set of operating system services. To deal with the lessamount of resources like registers in the older architectureas compared to the newer ones, we present a new registerallocation algorithm. The feasibility of the technique is establishedby simulating RABIT for its performance.