A dual-core 64b ultraSPARC microprocessor for dense server applications
Proceedings of the 41st annual Design Automation Conference
IMPACT OF NEGATIVE BIAS TEMPERATURE INSTABILITY ON PRODUCT PARAMETRIC DRIFT
ITC '04 Proceedings of the International Test Conference on International Test Conference
A dual-core 64b ultraSPARC microprocessor for dense server applications
Proceedings of the 41st annual Design Automation Conference
Online strategies for high-performance power-aware thread execution on emerging multiprocessors
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Factory: an object-oriented parallel programming substrate for deep multiprocessors
HPCC'05 Proceedings of the First international conference on High Performance Computing and Communications
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A processor core, previously implemented in a 0.25μm Al process, is redesigned for a 0.13μm Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applications. Deep submicron circuit design challenges, including negative bias temperature instability (NBTI), leakage and coupling noise, and L2 cache implementation are discussed.