Design of pipeline analog-to-digital converters via geometric programming
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A low-power design methodology for high-resolution pipelined analog-to-digital converters
Proceedings of the 2003 international symposium on Low power electronics and design
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
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In this paper a general method to design a pipelined ADC withminimum power consumption is presented. By expressing the totalpower consumption and the total input-referred noise of theconverter as functions of the capacitor values and the resolutions ofthe converter stages, an optimization algorithm is employed tocalculate the optimum values of these parameters, which lead tominimum power consumption while a specific noise requirement issatisfied. To determine the bias current values of operationalamplifiers an optimal choice for settling and slewing timeparameters is proposed. A practical design example is presented toshow the effectiveness of the proposed methodology.