Rules for analog and mixed-signal VHDL-AMS modeling

  • Authors:
  • Joachim Haase

  • Affiliations:
  • Fraunhofer-Institut Integrierte Schaltungen/Branch Lab Design Automation EAS, Zeunerstr, 38, D-01069 Dresden, Germany

  • Venue:
  • Languages for system specification
  • Year:
  • 2004

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Abstract

Since the standardization in 1999 the hardware description language VHDL-AMS is widely used for the modeling of digital, analog, and mixed-signal systems. On the one hand, the powerful language constructs allow a very flexible creation of user-defined models. On the other hand, it is possible to define simulation problems with correct syntax but without a solution. From a mathematical point of view some reasons of such problems are discussed and rules are established that may help to avoid these difficulties.