Migrating a CISC computer family onto RISC via object code translation
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Hardware/software co-simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
A hardware platform for VLIW based emulation of digital design (poster paper)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Methodology for hardware/software co-verification in C/C++ (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Binary Translation: Static, Dynamic, Retargetable?
ICSM '96 Proceedings of the 1996 International Conference on Software Maintenance
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper the application of Instruction Set Emulation for rapid prototyping of SoCs will be presented. The emulation works in a way that both the software and the hardware behaviour of the emulated processor core is reproduced cycle accurately. This requires the use of hardware and software components. The hardware component consists of a board containing a VLIW processor and FPGAs. The software component is an instruction set simulator of the core running on the VLIW processor. The FPGAs are used for emulating the SoC bus of this processor core. This way the simulation of an instruction set of a processor core has been extended to a real emulation of this core that can be used for rapid prototyping.