Alternative implementations of hybrid branch predictors
Proceedings of the 28th annual international symposium on Microarchitecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The impact of delay on the design of branch predictors
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design tradeoffs for the Alpha EV8 conditional branch predictor
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Compiler-directed instruction cache leakage optimization
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Dynamic Branch Prediction for a VLIW Processor
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Applying Decay Strategies to Branch Predictors for Leakage Energy Savings
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Branch prediction on demand: an energy-efficient solution
Proceedings of the 2003 international symposium on Low power electronics and design
Power Issues Related to Branch Prediction
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
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Leakage energy consumption is becoming an important design consideration with the scaling of technology. Besides caches, branch predictors are among the largest on-chip array structures and consume non-trivial leakage energy. This paper proposes two loop-based strategies to reduce the branch predictor leakage without impacting prediction accuracy, which is crucial for achieving high performance. The loop-based approaches exploit the fact that loops usually only contain a small number of instructions and hence fewer branch instructions. Consequently, all the non-active entries of branch predictors can be placed into the low leakage mode during the loop execution for leakage energy savings. Compilers can annotate this information and pass it to the processor for reducing leakage at runtime. Compared to the recently-proposed decay-based approach, our experimental results show that the loop-based approach can extract 16.2% more branch predictor idleness on average, leading to more leakage energy savings without impacting the branch prediction accuracy and performance.