Branch prediction techniques for low-power VLIW processors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Loop-based leakage control for branch predictors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Reducing branch predictor leakage energy by exploiting loops
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Tree traversal scheduling: a global instruction scheduling technique for VLIW/EPIC processors
LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
| Hi-index | 0.00 |
This paper describes the design of a dynamic branch predictor for a VLIW processor. The developed branch predictor predicts the direction of a branch, i.e., taken or not taken, and in the case of taken prediction, it predicts the issue-slot that contains the taken branch. This information is used to perform the BTB lookup. We compare this method against a typical superscalar branch predictor and against a branch predictor developed for VLIWs by Intel and HP. For a 2K entry BHT, 512 entry BTB, gshare branch predictor we obtain a next pc misprediction rate of 7.83%, while a traditional superscalar-type branch predictor of comparable costs achieves 10.3% and the Intel/HP predictor achieves 9.31%. In addition, we propose to have both predicted and delayed branches in the ISA and let the compiler select which type to apply. Simulations show performance improvements of 2-7% for benchmarks that are well known for their high misprediction rates. This paper also contributes an experiment to determine whether speculative update in the fetch stage and correction of mispredictions is necessary for VLIWs, instead of updating when branches are resolved. Experiments show that the performance advantage of speculative updating is small.