Supporting multiple-input, multiple-output custom functions in configurable processors
Journal of Systems Architecture: the EUROMICRO Journal
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Vectorized AES Core for High-throughput Secure Environments
High Performance Computing for Computational Science - VECPAR 2008
Polymorphic architectures: from media processing to supercomputing
CompSysTech '09 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing
M2E: a multiple-input, multiple-output function extension for RISC-Based extensible processors
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
MP-Tomasulo: A Dependency-Aware Automatic Parallel Execution Engine for Sequential Programs
ACM Transactions on Architecture and Code Optimization (TACO)
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We present a prototype design of the MOLEN polymorphic processor, a CCM based on the co-processor architectural paradigm. The Xilinx Virtex II Pro technology is used as a prototyping platform. Experimental results prove the viability of the MOLEN concept. More precisely, the MPEG-2 application is accelerated very closely to its theoretical limits by implementing SAD, DCT and IDCT in reconfigurable hardware. The MPEG-2 encoder overall speedup is in the range between 2.80 and 2.96. The speedup of the MPEG-2 decoder varies between 1.56 and 1.63.