Data networks
Computation of cyclic redundancy checks via table look-up
Communications of the ACM
Weighted sum codes for error detection and their comparison with existing codes
IEEE/ACM Transactions on Networking (TON)
Comments on “Weighted sum codes for error detection and their comparison with existing codes”
IEEE/ACM Transactions on Networking (TON)
Fast software implementation of error detection codes
IEEE/ACM Transactions on Networking (TON)
Performance of checksums and CRC's over real data
IEEE/ACM Transactions on Networking (TON)
Practical Algorithms for Programmers
Practical Algorithms for Programmers
A Tutorial on CRC Computations
IEEE Micro
A unified link-layer fault-tolerant architecture for network-based many-core embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
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Binary CRCs are very effective for error detection, but their software implementation is not very efficient. Thus, many binary non-CRC codes (which are not as strong as CRCs, but can be more efficiently implemented in software) are proposed as alternatives to CRCs. The non-CRC codes include WSC, CXOR, one's-complement checksum, Fletcher checksum, and block-parity code. In this paper, we present a general algorithm for constructing a family of binary error-detection codes. This family is large because it contains all these non-CRC codes, CRCs, perfect codes, as well as other linear and nonlinear codes. In addition to unifying these apparently disparate codes, our algorithm also generates some non-CRC codes that have minimum distance 4 (like CRCs) and efficient software implementation.