A parallel algorithm for constructing reduced visibility graph and its FPGA implementation

Authors:
K. Sridharan;T. K. Priya
Affiliations:
Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600 036, India;Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600 036, India
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2004

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Abstract

A central geometric structure in applications such as robotic path planning and hidden line elimination in computer graphics is the visibility graph. A new parallel algorithm to construct the reduced visibility graph in a convex polygonal environment is presented in this paper. The computational complexity is O(p2log(n/p)) where p is the number of objects and n is the total number of vertices. A key feature of the algorithm is that it supports easy mapping to hardware. The algorithm has been simulated (and verified) using C. Results of hardware implementation show that the design operates at high speed requiring only small space. In particular, the hardware implementation operates at approximately 53 MHz and accommodates the reduced visibility graph of an environment with 80 vertices in one XCV3200E device.