An FPGA-based VLIW processor with custom hardware execution
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
EURASIP Journal on Applied Signal Processing
A design automation and power estimation flow for RFID systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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This paper presents a power estimation and optimization approach in the early stage of behavioral synthesis for unscheduled data-dominated circuits. A methodology for estimating the power consumption of every module in the system is developed using an automatic construction of a novel switching table and the power table. An integer linear programming model is presented to reduce the energy consumption of the circuit through concurrent module selection, binding, and scheduling for a non-scheduled data path. Experimental results of six data-dominated benchmarks show that our technique achieves an average of 29.8% energy savings compared to a traditional area optimal synthesis algorithm where energy is not considered. Additionally, this approach consumes on the average 24.0% and 20.3% less energy compared to two other power-oriented optimization strategies respectively.