Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP)

Authors:
Anru Wang;Wayne Dai
Affiliations:
University of California, Santa Cruz;University of California, Santa Cruz
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

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Abstract

This paper presents a cost-effective area-IO DRAM (aDRAM)/Logic integration implemented with CLC (Chip-Laminate-Chip)-based System-in-a-Package (SiP) technology. By inserting 512 area-IOs into the aDRAM, the bandwidth of the area-IO DRAM can achieve 10GB/s when working under 166MHz. An interface module with configurable IO width was also developed to make this implementation platform adoptable by various applications. A performance analysis, including bandwidth and power is also presented in this paper. It is demonstrated that area-IO DRAM/Logic integration with SiP technology provides a significant cost-effective implementation methodology compared with embedded DRAM and off-chip DRAM.