A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dynamic zero compression for cache energy reduction
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Frequent value locality and value-centric data cache design
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Reducing cache misses by application-specific re-configurable indexing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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We propose an energy-efficient architecture for instruction caches that relies on dynamic zero compression (DZC), that is, the possibility of reading and writing a single bit for every zero-valued byte [5]. We enhance the basic DZC by using a simple bit permutation to increase the number of zero-valued bytes, so that the corresponding overhead is negligible. The derivation of an effective permutation relies on a heuristic zero clustering algorithm that is based on the knowledge of the memory reference access trace, thus making this solution suitable for application-specific embedded systems. The architecture proposed in this work makes possible the application of zero compression to instruction caches; experiments showed an increase of zero clusters of more than 70% on average, which translates into a 10% improvement in dynamic energy savings with respect to DZC.