Design and verification of fault tolerant systems with CSP

  • Authors:
  • Jan Peleska

  • Affiliations:
  • DST Deutsche System-Technik GmbH, Edisonstrasse 3, W-2300 Kiel 14, Federal Republic of Germany

  • Venue:
  • Distributed Computing
  • Year:
  • 1991

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Abstract

By means of an example, we present a formal method based on CSP to design fault tolerant systems. This method combines algebraic and assertional techniques to achieve complete formal verification of the fault tolerant system's correctness properties. Verification steps are executed in parallel with top-down design, so that correctness proofs can be clearly structured and their completeness easily checked. In this way formal verification is applicable not only to small examples but to reasonably large systems.