Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-parallel Architecture
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC in wireless environments
IEEE Transactions on Circuits and Systems for Video Technology
A low-power multiplier with the spurious power suppression technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BZ-FAD: a low-power low-area multiplier based on shift-and-add architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposes an efficient Spurious Power Suppression Technique (SPST) and its applications on an MPEG-4 AVC/H.264 transform coding design. There are three techniques addressed in this paper, which are (1) the SPST, (2) the direct 2-D algorithm, and (3) the interlaced I/O schedule to solve the design challenges induced by both the real-time processing and low-power requirements. The major novelty of this paper is implementing the SPST concept on the transform architecture for H.264, which save 31.9% power consumption at the cost of 20.9% area price. Moreover, the proposed transform design also possesses 60.05% higher hardware efficiency through the TPUA index than the existing designs