A scalable and high performance software iSCSI implementation
FAST'05 Proceedings of the 4th conference on USENIX Conference on File and Storage Technologies - Volume 4
WSEAS TRANSACTIONS on COMMUNICATIONS
WSEAS Transactions on Information Science and Applications
Effectiveness data transmission error detection using check sum control for military application
MAMECTIS'08 Proceedings of the 10th WSEAS international conference on Mathematical methods, computational techniques and intelligent systems
Performance increase of error control operation on data transmission
NTMS'09 Proceedings of the 3rd international conference on New technologies, mobility and security
High speed CRC with 64-bit generator polynomial on an FPGA
ACM SIGARCH Computer Architecture News
Towards transparent hardening of distributed systems
Proceedings of the 9th Workshop on Hot Topics in Dependable Systems
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A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optimizing their memory requirement to meet the constraints of specific computer architectures. In addition, our algorithms can be implemented in software using commodity processors instead of specialized parallel circuits. We use this framework to design two efficient algorithms that run in the popular Intel IA32 processor architecture. First, a ýslicing-by-4ý algorithm doubles the performance of existing software-based, table-driven CRC implementations based on the Sarwate [12] algorithm while using a 4K cache footprint. Second, a ýslicing-by-8ý algorithm triples the performance of existing software-based CRC implementations while using an 8K cache footprint.