Performance increase of error control operation on data transmission

Authors:
Nikolaos G. Bardis;Athanasios Drigas;Oleksandr P. Markovskyi
Affiliations:
Department of Mathematics and Engineering Science, University of Military Education, Hellenic Army Academy and Net Media Lab of Institute of Informatics & Telecommunications, N.C.S.R. Demokrit ...;N.C.S.R. Demokritos, Telecoms and Net Media Lab;Department of Computer Engineering, National Technical University of Ukraine, Polytechnic Institute of Kiev
Venue:
NTMS'09 Proceedings of the 3rd international conference on New technologies, mobility and security
Year:
2009

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Abstract

In this paper a new approach is proposed to increase the performance of the operation of error control on data transmission. Specifically, a hardware structure for parallel Cyclic Redundancy Check (CRC) calculation is developed to speed up the error control operation of data transmission. Based on a study of the properties of both CRC and Check Sum (CS) a new error detecting scheme is developed which combines CRC and CS. Also it is shown that the proposed error detecting scheme ensures high reliability and performance of the error control operation on data transmission in comparison to CRC alone.