Mitigating soft error failures for multimedia applications by selective data protection
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach
MM '08 Proceedings of the 16th ACM international conference on Multimedia
Partially protected caches to reduce failures due to soft errors in multimedia applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cache vulnerability equations for protecting data in embedded processor caches from soft errors
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Partitioning techniques for partially protected caches in resource-constrained embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Microprocessors & Microsystems
Smart cache cleaning: energy efficient vulnerability reduction in embedded processors
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Enabling energy efficient reliability in embedded systems through smart cache cleaning
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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With the nano-scale VLSI technology andsystem-on-chip (SOC) design methodology, the reliability has become one major challenge in SOCs. Especially, embedded memory cores heavily impact on the reliability of SOCs. Error detection and correction (EDAC) techniques are well-known methodologies for detecting and correcting soft errors of random access memories. However, conventional EDAC techniques cannot effectively be applied to embedded memory cores with partial-write operation. This paper presents an EDAC scheme for embedded memory cores with partial-write operation. The area cost for implementing the proposed EDAC scheme in an 8K 脳 64-bit SRAM core with half-word parity (i.e., two parity bits for each word) is about 21% based on 0.18µm TSMC standard cells.