Partially protected caches to reduce failures due to soft errors in multimedia applications

Authors:
Kyoungwoo Lee;Aviral Shrivastava;Ilya Issenin;Nikil Dutt;Nalini Venkatasubramanian
Affiliations:
Department of Computer Science, University of California at Irvine, Irvine, CA;Department of Computer Science and Engineering, Arizona State University, Tempe, AZ;Department of Computer Science, University of California at Irvine, Irvine, CA;Department of Computer Science, University of California at Irvine, Irvine, CA;Department of Computer Science, University of California at Irvine, Irvine, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

Citing 7
Cited 4

A data cache with multiple caching strategies tuned to different types of locality

ICS '95 Proceedings of the 9th international conference on Supercomputing
The SimpleScalar tool set, version 2.0

ACM SIGARCH Computer Architecture News
Robust System Design with Built-In Soft-Error Resilience

Computer
Soft Errors in Advanced Computer Systems

IEEE Design & Test
An Error Detection and Correction Scheme for RAMs with Partial-Write Function

MTDT '05 Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing
Compilation techniques for energy reduction in horizontally partitioned cache architectures

Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
MiBench: A free, commercially representative embedded benchmark suite

WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop

Partitioning techniques for partially protected caches in resource-constrained embedded systems

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Smart cache cleaning: energy efficient vulnerability reduction in embedded processors

CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures

ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Enabling energy efficient reliability in embedded systems through smart cache cleaning

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies

Quantified Score

Hi-index	0.00

Visualization

Abstract

With advances in process technology, soft errors are becoming an increasingly critical design concern. Owing to their large area, high density, and low operating voltages, caches are worst hit by soft errors. Based on the observation that in multimedia applications, not all data require the same amount of protection from soft errors, we propose a partially protected cache (PPC) architecture, in which there are two caches, one protected and the other unprotected at the same level of memory hierarchy. We demonstrate that as compared to the existing unprotected cache architectures, PPC architectures can provide 47 times reduction in failure rate, at only 1% runtime and 3% power overheads. In addition, the failure rate reduction obtained by PPCs is very sensitive to the PPC cache configuration. Therefore, this observation provides an opportunity for further improvement of the solution by correctly parameterizing the PPC configurations. Consequently, we develop design space exploration (DSE) strategies to discover the best PPC configuration. Our DSE technique can reduce the exploration time by more than six times as compared to an exhaustive approach.