Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards
Proceedings of the conference on Design, automation and test in Europe - Volume 3
High Level Fault Injection for Attack Simulation in Smart Cards
ATS '04 Proceedings of the 13th Asian Test Symposium
Tamper resistance: a cautionary note
WOEC'96 Proceedings of the 2nd conference on Proceedings of the Second USENIX Workshop on Electronic Commerce - Volume 2
System level power profile analysis and optimization for smart cards and mobile devices
Proceedings of the 2008 ACM symposium on Applied computing
Power profile estimation and compiler-based software optimization for mobile devices
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Software power peak reduction on smart card systems based on iterative compiling
EUC'07 Proceedings of the 2007 conference on Emerging direction in embedded and ubiquitous computing
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Smart cards are embedded systems which are used in an increasing number of secure applications. As they store and deal with confidential and secret data many attacks are performed on these cards to reveal this private information. Consequently, the security demands on smart cards are very high. It is mandatory to evaluate the security of the design but this is performed often very late in the design process or when the chip has already been manufactured. This paper presents a hierarchical security attack simulation flow for smart card designs where security attacks can be simulated in the processor specific model at transaction layer 1 in SystemC. Therefore, the power consumption profile is analyzed at this level. Preliminary results show that this analysis at high abstraction level can be used to determine vulnerabilities of the system to security attacks. Moreover, points to insert software countermeasures can easily be identified.