A stream chip-multiprocessor for bioinformatics
ACM SIGARCH Computer Architecture News
Pairwise Distance Matrix Computation for Multiple Sequence Alignment on the Cell Broadband Engine
ICCS '09 Proceedings of the 9th International Conference on Computational Science: Part I
A Massively Parallel Architecture for Bioinformatics
ICCS '09 Proceedings of the 9th International Conference on Computational Science: Part I
MT-clustalW: multithreading multiple sequence alignment
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Reconfigurable multiprocessor systems: a review
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
HLS tools for FPGA: faster development with better performance
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Biological sequence analysis with hidden markov models on an FPGA
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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Molecular Biologists frequently compute multiple sequence alignments (MSAs) to identify similar regions in protein families. Progressive alignment is a widely used approach to compute MSAs. However, aligning a few hundred sequences by popular progressive alignment tools requires several hours on sequential computers. Due to the rapid growth of biological sequence databases biologists have to compute MSAs in a far shorter time. In this paper we present a new approach to MSA on reconfigurable hardware platforms to gain high performance at low cost. To derive an efficient mapping onto this type of architecture, fine-grained parallel processing elements (PEs) have been designed. Using this PE design as a building block we have constructed a linear systolic array to perform a pairwise sequence distance computation using dynamic programming. This results in an implementation with significant runtime savings on a standard off-the-shelf FPGA.