Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The UCSC Kestrel Parallel Processor
IEEE Transactions on Parallel and Distributed Systems
Multiple Sequence Alignment on an FPGA
ICPADS '05 Proceedings of the 11th International Conference on Parallel and Distributed Systems - Workshops - Volume 02
COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
IEEE Transactions on Computers
Integrating FPGA acceleration into HMMer
Parallel Computing
Massively Parallelized DNA Motif Search on the Reconfigurable Hardware Platform COPACOBANA
PRIB '08 Proceedings of the Third IAPR International Conference on Pattern Recognition in Bioinformatics
High Performance Computing for Visualisation and Image Analysis
IVIC '09 Proceedings of the 1st International Visual Informatics Conference on Visual Informatics: Bridging Research and Practice
Optimizing investment strategies with the reconfigurable hardware platform RIVYERA
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
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Today's general purpose computers lack in meeting the requirements on computing performance for standard applications in bioinformatics like DNA sequence alignment, error correction for assembly, or TFBS finding. The size of DNA sequence databases doubles twice a year. On the other hand the advance in computing performance per unit cost only doubles every 2 years. Hence, ingenious approaches have been developed for putting this discrepancy in perspective by use of special purpose computing architectures like ASICs, GPUs, multicore CPUs or CPU Clusters. These approaches suffer either from being too application specific (ASIC and GPU) or too general (CPU-Cluster and multicore CPUs). An alternative is the FPGA, which outperforms the solutions mentioned above in case of bioinformatic applications with respect to cost and power efficiency, flexibility and communication bandwidths. For making maximal use of the advantages, a new massively parallel architecture consisting of low-cost FPGAs is presented.