Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes
IEEE Transactions on Computers
An efficient, fully adaptive deadlock recovery scheme: DISHA
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
IEEE Transactions on Parallel and Distributed Systems
An algorithm for distributed computation of a spanningtree in an extended LAN
SIGCOMM '85 Proceedings of the ninth symposium on Data communications
Performance evaluation of a new routing strategy for irregular networks with source routing
Proceedings of the 14th international conference on Supercomputing
High-Performance Routing in Networks of Workstations with Irregular Topology
IEEE Transactions on Parallel and Distributed Systems
A General Theory for Deadlock-Free Adaptive Routing Using a Mixed Set of Resources
IEEE Transactions on Parallel and Distributed Systems
Boosting the Performance of Myrinet Networks
IEEE Transactions on Parallel and Distributed Systems
TNet: A Reliable System Area Network
IEEE Micro
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Layered Shortest Path (LASH) Routing in Irregular System Area Networks
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Virtual Channel Multiplexing in Networks of Workstations with Irregular Topology
HIPC '98 Proceedings of the Fifth International Conference on High Performance Computing
Effective Methodology for Deadlock-Free Minimal Routing in InfiniBand Networks
ICPP '02 Proceedings of the 2002 International Conference on Parallel Processing
An Effective Methodology to Improve the Performance of the Up*/Down* Routing Algorithm
IEEE Transactions on Parallel and Distributed Systems
A proposal for managing ASI fabrics
Journal of Systems Architecture: the EUROMICRO Journal
ICCS '08 Proceedings of the 8th international conference on Computational Science, Part I
Implementing a Change Assimilation Mechanism for Source Routing Interconnects
Euro-Par '09 Proceedings of the 15th International Euro-Par Conference on Parallel Processing
A general methodology for direction-based irregular routing algorithms
Journal of Parallel and Distributed Computing
Routing-contained virtualization based on Up*/Down* forwarding
HiPC'07 Proceedings of the 14th international conference on High performance computing
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
Tree-turn routing: an efficient deadlock-free routing algorithm for irregular networks
The Journal of Supercomputing
Topology Agnostic Dynamic Quick Reconfiguration for Large-Scale Interconnection Networks
CCGRID '12 Proceedings of the 2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012)
An efficient, low-cost routing framework for convex mesh partitions to support virtualization
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
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Freedom from deadlock is a key issue in Cut-Through, Wormhole, and Store and Forward networks, and such freedom is usually obtained through careful design of the routing algorithm. Most existing deadlock-free routing methods for irregular topologies do, however, impose severe limitations on the available routing paths. We present a method called Layered Routing, which gives rise to a series of routing algorithms, some of which perform considerably better than previous ones. Our method groups virtual channels into network layers and to each layer it assigns a limited set of source/destination address pairs. This separation of traffic yields a significant increase in routing efficiency. We show how the method can be used to improve the performance of irregular networks, both through load balancing and by guaranteeing shortest-path routing. The method is simple to implement, and its application does not require any features in the switches other than the existence of a modest number of virtual channels. The performance of the approach is evaluated through extensive experiments within three classes of technologies. These experiments reveal a need for virtual channels as well as an improvement in throughput for each technology class.