VOIQ: A Practical High-Performance Architecture for the Implementation of Single-Buffered Routers

Authors:
Ximing Hu;Jing Qu;Yinhai Li;Binqiang Wang
Affiliations:
Air Force Engineering University, China;National Digital Switching System Engineering and Technological R&D Center;National Digital Switching System Engineering and Technological R&D Center;National Digital Switching System Engineering and Technological R&D Center
Venue:
HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
Year:
2005

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Abstract

In order to find a more tractable and practical architecture for high-performance routers within current technology and market constraints, the High- Performance Networking Group (HPNG) of Stanford University proposed to build a router just with single stage of buffering, i.e. the scheme of Single-Buffered (SB) routers. Concretely, two different designs of SB routers were proposed by HPNG: one of which was Parallel Shared Memory (PSM) router and the other was Distributed Shared Memory (DSM) router. Although the notion of Single-Buffered routers deserves full credit, the results of HPNG seem just theoretical rather than practical. In this paper, we attempt to make high-performance SB routers practical by introducing a new architecture for the shared memories. We call the resulting SB router as Virtual Output and Input Queued (VOIQ) router. We show that the scheme of VOIQ can eliminate the need for centralized memory management algorithms and allow a fully distributed implementation of SB routers with rich QoS guarantees and the ability to support variable-length packets while retaining low total memory bandwidth and complexity of processing and communication.