Topology selection for energy minimization in embedded networks

Authors:
Dexin Li;Pai H. Chou;Nader Bagherzadeh
Affiliations:
University of California, Irvine, CA;University of California, Irvine, CA;University of California, Irvine, CA
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

Citing 1
Cited 2

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FireWire system architecture: IEEE 1394

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GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing

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Abstract

The trend towards distributed, networked embedded systems is changing the way power should be managed. Power consumed by bus and network interfaces now matches if not surpasses that of the CPU and is thus becoming a prime candidate for reduction. This paper explores energy-efficient bus topologies as a new technique for global power optimization of embedded systems that are interconnected by high-speed serial network-like busses such as FireWire and a new generation of SoC buses. Our grammar-based representation for these networks enables selection of energy-efficient bus topologies. Experimental results show 15-20% energy saving on the network interfaces without sacrificing system performance.