Ray tracing animated scenes using coherent grid traversal
ACM SIGGRAPH 2006 Papers
Ray tracing deformable scenes using dynamic bounding volume hierarchies
ACM Transactions on Graphics (TOG)
Efficient data reduction and cache-coherent techniques toward real-time performance
ACM SIGGRAPH 2007 courses
Memory efficient ray tracing with hierarchical mesh quantization
Proceedings of Graphics Interface 2010
Shallow bounding volume hierarchies for fast SIMD ray tracing of incoherent rays
EGSR'08 Proceedings of the Nineteenth Eurographics conference on Rendering
ReduceM: interactive and memory efficient ray tracing of large models
EGSR'08 Proceedings of the Nineteenth Eurographics conference on Rendering
| Hi-index | 0.00 |
Bounding volume hierarchies (BVHs) are an effective method for improving the performance of ray tracing algorithms. A BVH consists of a tree of bounding volumes enclosing the objects within the scene. Bounding volumes are typically axis-aligned bounding boxes, or AABBs. This research first presents up-to-date surveys of literature relevant to BVHs and ray tracing hardware. A new method is derived for determining if a ray and an AABB overlap using Plücker coordinates. When used in a BVH, this method improves ray tracing performance by up to 27%. A reduced-precision, hierarchical, integer representation for the BVH's AABB coordinates is investigated that reduces BVH memory requirements by 63% to 75%. Unfortunately, significant computational overhead is incurred because the integer representation must be converted back to floating point during ray tracing. Coherent ray tracing is employed to amortize the conversion cost over many rays, reducing the overhead to a negligible level. Lastly, reduced-precision, integer ray-AABB overlap tests are derived and hardware designs are compared to the equivalent floating-point tests. These integer tests are guaranteed to produce identical images to the higher-precision floating-point tests because they correctly handle uncertainty clue to numerical imprecision. The integer tests are shown to reduce the circuit size and complexity of a hardware ray-AABB test by roughly half.