SPEClite: using representative samples to reduce SPEC CPU2000 workload

Authors:
R. Todi
Affiliations:
Syst. VLSI Technol. Organ., Hewlett Packard, Cupertino, CA, USA
Venue:
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Year:
2001

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Abstract

An execution-driven microarchitecture-accurate microprocessor simulator requires a complex software program. The simulator must be highly detailed and accurate if it is used for microarchitecture design evaluation. The detail and accuracy comes at the high cost of enormous simulation time. A simulator that models a modern super-scalar processor is 10/sup 5/ to 10/sup 6/ times slower than the actual hardware being modeled. Running a benchmark in full microarchitecture mode (UA) can be execution time prohibitive. Hence, simulators are less effective than they could be due to slowness in the simulated result. This paper presents a methodology of selecting and executing representative samples that reduce the simulation time and maintains the accuracy of the simulated result. We illustrate our methodology using the Vortex benchmark from the SPEC CPU2000 suite (SPEC2K).