Code restructuring for improving cache performance of MPSoCs

  • Authors:

  • G. Chen;M. Kandemir

  • Affiliations:

  • Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA, USA;Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA, USA

  • Venue:
  • ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
  • Year:
  • 2005

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Abstract

One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely costly from both performance and power angles. While conventional data locality optimization techniques can be used for improving data access pattern of each processor independently, such techniques usually do not consider locality for shared data. This paper proposes a strategy that reduces the number of off-chip references due to shared data. It achieves this goal by restructuring a parallelized application code in such a fashion that a given data block is accessed by parallel processors within the same time frame, so that its reuse is maximized while it is in the on-chip memory space. This tends to minimize the number of off-chip references since the accesses to a given data block are clustered within a short period of time during execution. Our approach employs a polyhedral tool that helps us isolate computations that manipulate a given data block.