Heads and tails: a variable-length instruction format supporting parallel fetch and decode
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
A 333-MHz dual-MAC DSP architecture for next-generation wireless applications
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Journal of Signal Processing Systems
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As the concurrent functional units in media processors increase continuously to meet the performance needs, the required access (i.e. read or write) ports of the centralized register file (RF) multiply rapidly and cannot be efficiently implemented. We propose a novel ring-structure RF, which is composed of register sub-blocks identical to the RF for a single functional unit. Data exchanges among functional units occur on the switch network of the ring registers. The proposed RF has been integrated into a four-way VLIW DSP processor successfully that demonstrates its effectiveness in DSP kernels. The synthesis result shows that our proposed ring-structure RF saves 91.88% silicon area of the centralized one, while reducing its access time by 77.35%.