Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations

Authors:
Yang Song;Zhenyu Liu;Takeshi Ikenaga;Satoshi Goto
Affiliations:
The authors are with Graduate School of Information, Production and Systems, Waseda University, Kitakyushu-shi, 808--0135 Japan. E-mail: syang@asagi.waseda.jp,;The author is with Kitakyushu Foundation for the Advancement of Industry Science and Technology, Kitakyushu-shi, 808--0135 Japan.;The authors are with Graduate School of Information, Production and Systems, Waseda University, Kitakyushu-shi, 808--0135 Japan. E-mail: syang@asagi.waseda.jp,;The authors are with Graduate School of Information, Production and Systems, Waseda University, Kitakyushu-shi, 808--0135 Japan. E-mail: syang@asagi.waseda.jp,
Venue:
IEICE - Transactions on Information and Systems
Year:
2007

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Abstract

This paper presents two hardware-friendly low-power oriented fast motion estimation (ME) algorithms and their VLSI implementations. The basic idea of the proposed partial distortion sorting (PDS) algorithm is to disable the search points which have larger partial distortions during the ME process, and only keep those search points with smaller ones. To further reduce the computation overhead, a simplified local PDS (LPDS) algorithm is also presented. Experiments show that the PDS and LPDS algorithms can provide almost the same image quality as full search only with 36.7% computation complexity. The proposed two algorithms can be integrated into different FSBMA architectures to save power consumption. In this paper, the 1-D inter ME architecture [12] is used as an detailed example. Under the worst working conditions (1.62 V, 125°C) and 166 MHz clock frequency, the PDS algorithm can reduce 33.3% power consumption with 4.05 K gates extra hardware cost, and the LPDS can reduce 37.8% power consumption with 1.73 K gates overhead.