Modeling semiconductor tools for small lotsize FAB simulations

Authors:
Kilian Schmidt;Jörg Weigang;Oliver Rose
Affiliations:
AMD Saxony LLC & Co. KG, Dresden, Germany;AMD Saxony LLC & Co. KG, Dresden, Germany;Technical University of Dresden, Dresden, Germany
Venue:
Proceedings of the 38th conference on Winter simulation
Year:
2006

Citing 0
Cited 3

Sensitivity analysis on causal events of WIP bubbles by a log-driven simulator

Proceedings of the 39th conference on Winter simulation: 40 years! The best is yet to come
Automated generation of analytical process time models for cluster tools in semiconductor manufacturing

Proceedings of the Winter Simulation Conference
On the fidelity of the ax+b equipment model for clustered photolithography scanners in fab-level simulation

Proceedings of the Winter Simulation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

Short cycle times are critical to the success of semiconductor manufacturing. The addition of more and more mask layers leads to higher raw process times and makes short cycle times an increasingly challenging task. One cycle time reduction possibility semiconductor manufacturers now look at is lotsize reduction. A reduction in lotsize transfers directly into lower raw process times. Modeling and simulation are key to assess opportunities and risks of such an approach. This paper looks at the implications that follow from small lotsizes for tool models used for the assessment.